Rolf Drechsler Livres

Focusing on advancements in integrated circuits, the book presents innovative strategies for enhancing design reliability and testability, particularly in safety-critical applications. It explores formal techniques like the Satisfiability (SAT) problem and Bounded Model Checking (BMC) to tackle challenges related to test data volume and application time. Detailed discussions and extensive evaluations of these methods are provided, alongside industry-relevant benchmarks. The authors integrate these approaches into a unified framework with standardized software and hardware interfaces.

The book explores the realm of VLSI CAD, focusing on the ongoing challenge of solving complex optimization problems. It discusses various optimization techniques, highlighting those that have gained traction in practical applications over time, as well as those that have been overlooked. Through this examination, it aims to provide insights into the effectiveness and relevance of different optimization strategies within the field.

The book explores the innovative paradigm of one-pass synthesis in digital circuit design, addressing the inefficiencies of traditional multi-step processes that often lead to suboptimal results. It highlights the importance of integrating various design phases, such as utilizing layout information during logic synthesis and optimizing one level to better align with the next. By presenting examples of these techniques, the book provides insights into developing more efficient algorithms that enhance the quality of circuit designs while reducing time and costs associated with multiple iterations.

Focusing on digital systems, the text presents a comprehensive design and verification flow that emphasizes quality. It incorporates specialized verification techniques tailored to various levels of abstraction, ensuring a thorough assessment of verification quality. Each method is equipped with tools to measure its effectiveness, making it a valuable resource for those seeking to enhance the reliability and performance of digital designs.

The book delves into the challenges of formal verification in circuit design, particularly as the complexity of circuits increases with millions of transistors. It emphasizes the limitations of pure simulation and the benefits of leveraging regular structures in designs for easier verification. Highlighting the use of Word-Level Decision Diagrams (WLDDs), the text explains how these graph-based representations facilitate the verification of functions with a Boolean range and integer domain, making the process more efficient for complex designs like ALUs and multipliers.

The book addresses the challenges in designing and verifying increasingly complex integrated circuits. It analyzes current methodologies, identifies deficiencies, and proposes improvements in both design and verification processes. A comprehensive tool flow for Synthesis for Testability of SystemC descriptions is introduced, enabling fully testable circuits with efficient test pattern generation. Additionally, it presents a new paradigm for formal design verification, emphasizing design understanding and automated property generation, supported by empirical evaluations to enhance usability and robustness in design flows.

Focusing on Binary Decision Diagrams (BDDs), this book serves as an essential guide for both newcomers and seasoned professionals in VLSI CAD. It highlights the significance of BDDs in efficiently representing and manipulating Boolean functions, emphasizing their growing applications beyond CAD. Readers will gain insights into classical methods as well as innovative approaches for BDD minimization and implementation. This resource aims to keep industry and academic professionals updated on recent advancements and challenges in the field of BDDs.

This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

Diese Festschrift ist Professor Dr. Bernd Becker gewidmet, der am 19. Juli 2014 seinen 60. Geburtstag gefeiert hat. Bernd Becker ist seit Mitte der 1990er Jahre Professor für Rechnerarchitektur an der Albert-Ludwigs-Universität in Freiburg im Breisgau. Dort hat er über viele Jahre erfolgreich eine Arbeitsgruppe aufgebaut, die weltweit einen herausragenden Ruf besitzt. Zur vorliegenden Festschrift haben seine ehemaligen Mitarbeiter beigetragen, die bei ihm erfolgreich promoviert haben. Die Festschrift besteht aus zwei Teilen. Im ersten Teil gibt es individuelle Beiträge, die die ganze Breite darbieten, welche die Ehemaligen heute repräsentieren. Im zweiten Teil hat jeder der Absolventen eine wissenschaftliche Arbeit ausgewählt, die gemeinsam mit Bernd Becker entstanden ist.

This book presents the lecture notes of the 1st Summer School on Methods and Tools for the Design of Digital Systems, 2015, held in Bremen, Germany. The topic of the summer school was devoted to modeling and verification of cyber-physical systems. This covers several aspects of the field, including hybrid systems and model checking, as well as applications in robotics and aerospace systems. The main chapters have been written by leading scientists, who present their field of research, each providing references to introductory material as well as latest scientific advances and future research directions. This is complemented by short papers submitted by the participating PhD students.