Görschwin Fey Livres

The book addresses the challenges in designing and verifying increasingly complex integrated circuits. It analyzes current methodologies, identifies deficiencies, and proposes improvements in both design and verification processes. A comprehensive tool flow for Synthesis for Testability of SystemC descriptions is introduced, enabling fully testable circuits with efficient test pattern generation. Additionally, it presents a new paradigm for formal design verification, emphasizing design understanding and automated property generation, supported by empirical evaluations to enhance usability and robustness in design flows.

This book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers. Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages; Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level; Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.